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data sheet rev.1.0 21.11.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 1 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 2048 mb ddr3 l C sdram so - dimm 204 pin so - dimm s l n0 2g64 d 2b k 1 mt - xx r t 2gbyte in fbga t echnology rohs compliant *) the refresh rate has to be doubled when 85c data sheet rev.1.0 21.11.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 2 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 this swissbit module is an industry standard 204 - pin 8 - byte ddr3 sdram small outline dual - in - line memory module (so - dimm) which is organized as x64 high speed cmos memory arrays. the module uses internally configured oct al - bank ddr3 sdram devices. the module uses double data rate architecture to achieve high - speed operation. ddr3 sdram modules operate from a differential clock (ck and ck#). read and write accesses to a ddr3 sdram module is burst - oriented; accesses start at a selected location and conti nue for a programmed number of locations in a programmed sequence. the burst length is either four or eight locations. an auto precharge function can be enabled to provide a self - timed row precharge that is initiated at the end of a burst access. the ddr3 sdram devices have a multibank architecture which allows a concurrent operation that is providing a high effective bandwidth. a self refresh mode is provided and a power - saving power - down mode. all inputs and all full drive - strength outputs are sstl_15 c ompatible. the ddr3 sdram module uses the serial presence detect (spd) function implemented via serial eeprom using the standard i 2 c protocol. this nonvolatile storage device contains 256 bytes. the first 128 bytes are utilized by the so - dimm manufacturer (swissbit) to identify the module type, the modules organization and several timing parameters. the second 128 bytes are available to the end user. module configuration organization ddr3 sdrams used row addr. device bank addr. col umn addr. refresh module bank select 256 m x 64bit 8 x 256 m x 8bit ( 2048 m bit) 15 ba0, ba1, ba2 10 8k s0# module dimensions in mm 67.60 (long) x 30(high) x 3 . 80 [max] (thickness) timing parameters part number module density transfer rate clock cycle/data bit rate latency sl n02g64 d 2b k 1 mt - cc r t 2048 mb 10.6 gb/s 1. 5 ns /1 333 mt/s 9 - 9 - 9 sl n02g64 d 2b k 1 mt - dc r t 2048 mb 12.8 gb/s 1. 25 ns /1 600 mt/s 11 - 11 - 11 pin name a0 - 9, a11 C a14 address inputs a10/ap address input / autoprecharge bit ba0 C ba 2 bank address inputs dq0 C dq63 dat a input / output dm0 - dm7 input data mask dqs0 - dqs7 data strobe, positive line dqs0# - dqs7# data strobe, negative line (only used when differential data strobe mode is enabled) ras# row address strobe cas# column address strobe we# write enable ck e 0 clock enable s0# chip select ck0 clock inputs, positive line figure 1: mechanical dimensions
data sheet rev.1.0 21.11.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 3 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 ck0# clock inputs, negative line event# temperature event: the event# pin is asserted by the temperature sensor when critical v dd supply voltage ( 1.35v - 0.067v/+0.1v and 1.5v 0.075v ) v ref dq reference voltage: dq, dm (vdd/2) v ref ca reference voltage: control, command, and address (vdd/2) v ss ground v tt termination voltage: used for control, command, and address (vdd/2). v ddspd serial eeprom positive power supply scl serial clock for presence detect sda serial data out for presence detect sa0 C sa1 presence detect address inputs odt0 on - die termination nc no connection pin configuration frontside pin# symbol pin# symbol pin# symbol pin# symbol 1 v ref dq 53 dq19 103 ck 0 # 155 v ss 3 v ss 55 v ss 105 v dd 157 dq42 5 dq0 57 dq24 107 a10/ap 159 dq43 7 dq1 59 dq25 109 ba0 161 v ss 9 v ss 61 v ss 111 v dd 163 dq48 11 dm0 63 dm3 113 we# 165 dq49 13 v ss 65 v ss 115 cas# 167 v ss 15 dq2 67 dq26 117 v dd 169 dqs6# 17 dq3 69 dq27 119 a13 171 d qs6 19 v ss 71 v ss 121 nc ( s1# ) 173 v ss 21 dq8 key 123 v dd 175 dq50 23 dq9 73 cke0 125 nc (test) 177 dq51 25 v ss 75 v dd 127 v ss 179 v ss 27 dqs1# 77 nc 129 dq32 181 dq56 29 dqs1 79 ba2 131 dq33 183 dq57 31 v ss 81 v dd 133 v ss 185 v ss 33 dq10 83 a12/bc # 135 dqs4# 187 dm7 35 dq11 85 a9 137 dqs4 189 v ss 37 v ss 87 v dd 139 v ss 191 dq58 39 dq16 89 a8 141 dq34 193 dq59 41 dq17 91 a5 143 dq35 195 v ss 43 v ss 93 v dd 145 v ss 197 sa0 45 dqs2# 95 a3 147 dq40 199 v ddspd 47 dqs2 97 a1 149 dq41 201 sa1 49 v ss 99 v dd 151 v ss 203 v tt 51 dq18 101 ck 0 153 dm5 (sig): signal in brackets may be routed to the socket connector, but is not used on the module
data sheet rev.1.0 21.11.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 4 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 backside pin# symbol pin# symbol pin# symbol pin# symbol 2 v ss 54 v ss 104 nc (ck1#) 156 v ss 4 dq4 56 dq28 106 v dd 158 dq46 6 dq5 58 dq29 108 ba1 160 dq47 8 v ss 60 v ss 110 ras# 162 v ss 10 dqs0# 62 dqs3# 112 v dd 164 dq52 12 dqs0 64 dqs3 114 s0# 166 dq53 14 v ss 66 v ss 116 odt0 168 v ss 16 dq6 68 dq30 118 v dd 170 dm6 18 dq7 70 dq31 120 nc (odt1) 172 v ss 20 v ss 72 v ss 122 nc 174 dq54 22 dq12 key 124 v dd 176 dq55 24 dq13 74 nc (cke1) 126 v ref ca 178 v ss 26 v ss 76 v dd 128 v ss 180 dq60 28 dm1 78 nc (a15) 130 dq36 182 dq61 30 nc (reset#) 80 a14 132 dq37 184 v ss 32 v ss 82 v dd 134 v ss 186 dqs7# 34 dq14 84 a1 1 136 dm4 188 dqs7 36 dq15 86 a7 138 v ss 190 v ss 38 v ss 88 v dd 140 dq38 192 dq62 40 dq20 90 a6 142 dq39 194 dq63 42 dq21 92 a4 144 v ss 196 v ss 44 v ss 94 v dd 146 dq44 198 event# 46 dm2 96 a2 148 dq45 200 sda 48 v ss 98 a0 150 v ss 202 scl 50 dq22 100 v dd 152 dqs5# 204 v tt 52 dq23 102 nc (ck1) 154 dqs5 (sig): signal in brackets may be routed to the socket connector, but is not used on the module
data sheet rev.1.0 21.11.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 5 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 functional block diagramm 2048 mb ddr3 sdram sodimm, 1 rank and 8 components i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 d m d q s z q d 0 d q s c s i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 d m d q s z q d 1 d q s c s d q 0 d q 1 d q 2 d q 3 d q 5 d q 4 d q 6 d q 7 s 0 d q s 0 d q s 0 d m 0 d q s 1 d q s 1 d m 1 d q 8 d q 9 d q 1 0 d q 1 1 d q 1 3 d q 1 2 d q 1 4 d q 1 5 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 d m d q s z q d 2 d q s c s d q s 2 d q s 2 d m 2 d q 1 6 d q 1 7 d q 1 8 d q 1 9 d q 2 1 d q 2 0 d q 2 2 d q 2 3 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 d m d q s z q d 3 d q s c s d q s 3 d q s 3 d m 3 d q 2 4 d q 2 5 d q 2 6 d q 2 7 d q 2 9 d q 2 8 d q 3 0 d q 3 1 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 d m d q s z q d 4 d q s c s i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 d m d q s z q d 5 d q s c s d q 3 2 d q 3 3 d q 3 4 d q 3 5 d q 3 7 d q 3 6 d q 3 8 d q 3 9 d q s 4 d q s 4 d m 4 d q s 5 d q s 5 d m 5 d q 4 0 d q 4 1 d q 4 2 d q 4 3 d q 4 5 d q 4 4 d q 4 6 d q 4 7 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 d m d q s z q d 6 d q s c s d q s 6 d q s 6 d m 6 d q 4 8 d q 4 9 d q 5 0 d q 5 1 d q 5 3 d q 5 2 d q 5 4 d q 5 5 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 d m d q s z q d 7 d q s c s d q s 7 d q s 7 d m 7 d q 5 6 d q 5 7 d q 5 8 d q 5 9 d q 6 1 d q 6 0 d q 6 2 d q 6 3 v d d s p d s p d v d d / v d d q d 0 - d 7 v r e f d q v r e f c a d 0 - d 7 d 0 - d 7 d 0 - d 7 v s s b a 0 - b a 2 b a 0 - b a 2 : s d r a m d 0 - d 7 a 0 - a 1 4 a 0 - a 1 4 : s d r a m d 0 - d 7 r a s r a s : s d r a m d 0 - d 7 c a s c a s : s d r a m d 0 - d 7 w e w e : s d r a m d 0 - d 7 o d t 0 o d t : s d r a m d 0 - d 7 c k e 0 c k e : s d r a m d 0 - d 7 c k 0 c k : s d r a m d 0 - d 7 c k 0 c k : s d r a m d 0 - d 7 r e s e t r e s e t : s d r a m d 0 - d 7 n o t e s : 1 . d q - t o - i / o w i r i n g i s s h o w n a s r e c o m m e n d e d b u t m a y b e c h a n g e d . 2 . d q / d q s / d q s / o d t / d m / c k e / s r e l a t i o n s h i p m u s t b e m a i n t a i n e d a s s h o w n . 3 . d q , d m , d q s / d q s r e s i s t o r s : r e f e r t o a s s o c i a t e d t o p o l o g y d i a g r a m . 4 . r e f e r t o t h e a p p r o p r i a t e c l o c k w i r i n g t o p o l o g y u n d e r t h e d i m m w i r i n g d e t a i l s s e c t i o n o f t h e j e d e d d o c u m e n t . 5 . f o r e a c h d r a m , a u n i q u e z q r e s i s t o r i s c o n n e c t e d t o g n d . t h e z q r e s i s t o r i s 2 4 0 1 % . 6 . r e f e r t o a s s o c i a t e d f i g u r e f o r s p d d e t a i l s .
data sheet rev.1.0 21.11.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 6 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 maximum electrical dc characteristics parameter/ condition symbol min max units supply voltage v dd - 0.4 1.975 v i/o supply voltage v dd q - 0.4 1.975 v voltage on any pin relative to v ss v in , v out - 0.4 1.975 v input leakage current any input 0v v in v dd, v ref pin 0v v in 0.95v (all other pins not under test = 0v) i i a command/address ras#, cas#, we#, s#, cke - 16 16 ck, ck# - 16 16 dm - 2 2 output leakage current (dqs and odt are disabled; 0v v out v dd q ) i oz - 5 5 a dq, dqs, dqs# v ref leakage current ; v ref is on a valid level i vref - 8 8 a dc operating conditions parameter/ condition symbol min nom max units supply voltage v dd 1. 283 1. 3 5 1.450 v i/o supply voltage v dd q 1. 283 1. 3 5 1.450 v i/o refe rence voltage v ref 0.49 x v dd q 0.50 x v dd q 0.51x v dd q v i/o termination voltage (system) v tt 0.49 x v dd q - 20mv 0.50 x v dd q 0.51x v dd q +20mv v input high (logic 1) voltage v ih (dc 90 ) v ref + 90mv v dd q + 0.3 v input low (logic 0) voltage v il (dc 90 ) - 0.3 v ref C under 1.5v operation this ddr3l device operates in accordance to the following specification: sgn02g64d2bm1mt - xx rt ac input operating conditions parameter/ condition symbol min max units input high (logic 1) voltage v ih ( ac135 ) v ref + 135mv - v input low (logic 0) voltage v il (ac 135 ) - v ref C 135mv v capacitance at ddr3 data rates, it is recommended to simulate the performance of the module to achieve optimum values. when inductance and delay parameters associated with trace leng ths are used in simulations, they are significantly more accurate and realistic than a gross estimation of module capacitance. simulations can then render a considerably more accurate result. jedec modules are now designed by using simulations to close tim ing budgets.
data sheet rev.1.0 21.11.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 7 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 i dd specifications and conditions (0c t case + 85c; v dd q , v dd = 1.283v C 1.45v ) parameter & test condition symbol max. unit 1 2800 cl11 10600 cl9 operating current *) : one device bank active - precharge; t rc = t rc (i dd ); t ck = t ck (i dd ); cke is high, cs# is high between valid commands ; dq inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd0 480 440 ma operating current *) : one device bank; active - read - precharge; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t r c (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address inputs changing once every two clock cycles; data pattern is same as i dd4w i dd1 600 560 ma precharge power - down current: all device banks idle; pow er - down mode; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are floating at v ref fast exit i dd2p 264 224 ma slow exit 96 96 precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is h igh, cs# is high; all control and address bus inputs are not changing; dqs are floating at v ref i dd2q 264 224 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; all other control and address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd2n 280 240 ma active power - down current: all device banks open; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are floating at v ref (always fast exit) i dd3p 376 336 ma active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; all other control and address bus inputs are changing once eve ry two clock cycles; dq inputs changing once per clock cycle i dd3n 416 376 ma operating read current: all device banks open, continuous burst reads; one module rank active; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ) , t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd4r 1120 1000 ma
data sheet rev.1.0 21.11.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 8 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 parameter & test condition symbol max. unit 12800 cl1 1 10600 cl9 operating write current: all device banks open, continuous burst writes; one module rank active; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; addre ss bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd4w 1000 880 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval, cke is high, cs# is high between valid commands; all ot her control and address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd5 1520 1480 ma self refresh current: ck and ck# at 0v; cke 0.2v; all other control and address bus inputs are floating at v ref ; dq s are floating at v ref i dd6 96 96 ma operating current*) : four device bank interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) C 1 x t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address bus inputs are not changing during deselect; dq inputs changing once per clock cycle i dd7 1760 1640 ma *) value calculated as one module rank in this operating condition, and all other module ranks in idd2p (cke low ) mode. timing values used for i dd measurement i dd measurement conditions symbol 12800 cl11 10600 cl9 unit cl (i dd ) 11 9 t ck t rcd (i dd ) 13. 75 13. 5 ns t rc (i dd ) 48. 75 49. 5 ns t rrd (i dd ) 6 6 ns t ck (i dd ) 1.25 1.5 ns t ras min (i dd ) 35 36 ns t ras ma x (i dd ) 70 200 70 200 ns t rp (i dd ) 13. 75 13.5 ns t rfc (i dd ) 160 160 ns
data sheet rev.1.0 21.11.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 9 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 ddr3 sdram component electrical characteristics and recommended ac operating conditions (0c t case + 85c; v dd q , v dd = 1.283v C 1.45v ) ac characteristics 12800 cl11 10600 cl9 parameter symbol min max min max unit clock cycle time cl = 11 t ck (11) 1.25 - - - ns cl = 10 t ck (10) 1.5 <1.875 1.5 <1.875 cl = 9 t ck (9) 1.5 <1.875 1.5 <1.875 cl = 8 t ck (8) 1.875 <2.5 1.875 <2.5 cl = 7 t ck (7) 1.875 <2.5 1.875 <2.5 cl = 6 t ck (6) 2.5 3.3 2.5 3.3 cl = 5 t ck (5) 3.0 3.3 3.0 3.3 internal read command to first data t aa 13.75 - 13.5 - ck high - level width t ch (avg) 0.47 0. 53 0.47 0.53 t ck ck low - level width t cl (avg) 0.47 0.53 0.47 0.53 t ck data - out high - impedance window from ck/ck# t hz - 225 - 250 ps data - out low - impedance window from ck/ck# t lz - 450 225 - 500 250 ps dq and dm input setup time relative to dqs v ref =1v/ns t ds1v 1 60 - 180 - ps dq and dm input hold time relative to dqs v ref =1v/ns t dh1v 145 - 165 - ps dq and dm input pulse width ( for each input ) t dipw 360 - 400 - p s dqs, dqs# to dq skew, per access t dqsq - 100 - 125 ps dq - dqs hold, dqs to first dq to go non - valid, per access t qh 0.38 - 0.38 - t ck (avg) dqs input high pulse width t dqsh 0.45 0.55 0.45 0.55 t ck dqs input low pulse width t dqsl 0.45 0.55 0.45 0.55 t ck dqs, dqs# rising to/from ck, ck# t dqsck - 2 25 2 25 - 255 255 ps dqs, dqs# rising to/from ck , ck# when dll disabled t dqsck dll_dis 1 10 1 10 ns dqs falling edge to ck rising - setup time t dss 0. 18 - 0.2 - t ck dqs falling edge from ck rising - hold time t dsh 0. 18 - 0.2 - t ck dqs read preamble t rpre 0.9 note1 0.9 note1 t ck dqs read postamble t rpst 0.3 note2 0.3 note2 t ck dqs write preamble t wpre 0.9 - 0.9 - t ck dqs write postamble t wpst 0.3 - 0.3 - t ck positive dqs latching edge to associated clock edge t dqss - 0.2 7 + 0.2 7 - 0.25 + 0.25 t ck address and control input pulse width ( for each i nput ) t ipw 560 - 620 - ps ctrl, cmd, addr setup to ck, ck# t is(base) 45 - 65 - ps ctrl, cmd, addr setup to ck, ck# v ref @ 1v/ns t is(1v) 2 20 - 240 - ps 1 the maximum preamble is bound by t lzdqs (max) 2 the maximum postamble is bound by t hzdqs (max)
data sheet rev.1.0 21.11.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 10 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 ddr3 s dram component electrical characteristics and recommended ac operating conditions (continued) (0c t case + 85c; v dd q , v dd = 1.283v C 1.45v ) ac characteristics 12800 cl11 10600 cl9 parameter symbol min max min max unit ctrl, cmd, addr hold to ck, ck# t ih(base) 1 20 - 140 - ps ctrl, cmd, addr hold to ck, ck# v ref @ 1v/ns t ih(1v) 2 20 - 240 - ps cas# to cas# command delay t ccd 4 - 4 - t ck active to active (same bank) command period t rc 48.75 - 49.5 - ns active to active minimum command period t rrd max 4nck,6ns max 4nck,6ns ns active to read or write delay t rcd 13. 7 5 - 13. 5 - ns four ban k activate period 1k page size t faw 30 - 30 - ns 2k page size 4 0 - 45 - active to precharge command t ras 3 5 70 t rtp max 4nck,7.5ns - max 4nck,7.5ns - ns write recovery time t wr 15 - 15 - ns auto precharge write recovery + precharge time t dal t wr + t rp /t ck - t wr + t rp /t ck - ns internal write to read command delay t wtr max 4nck,7.5ns - max 4nck,7.5ns - ns precharge command period t rp 13. 7 5 - 13. 5 - ns load mode command cycle time t mrd 4 - 4 - t ck refresh to active or refresh to refresh command interval t rfc 160 70 0 c t case 85 c t refi - 7.8 - 7.8 s 85 c < t case 95 c t refi (it) - 3.9 - 3.9 rtt turn - on from odtl on reference t aon - 2 25 2 25 - 250 250 ps rtt turn - on from odtl off reference t aof 0.3 0.7 0.3 0.7 t ck asynchronous rtt turn - on delay (power down with d ll off) t aonpd 2 8,5 2 8,5 ns asynchronous rtt turn - off delay (power down with dll off) t aofpd 2 8,5 2 8,5 ns rtt dynamic change skew t adc 0.3 0.7 0.3 0.7 t ck exit self refresh to commands not requiring a locked dll t xs max 5nck,tr fc + 10ns - max 5nck, tr fc + 10ns - ns write levelling setup from rising ck, ck# crossing to rising dqs, dqs# crossing t wls 1 65 - 195 - ps write levelling setup from rising dqs, dqs# crossing to rising ck, ck# crossing t wlh 165 - 195 - ps first dqs, dqs# rising edge t wlmrd 40 - 40 - t ck dqs, dqs# delay t wldqsen 25 - 25 - t ck
data sheet rev.1.0 21.11.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 11 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 ddr3 sdram component electrical characteristics and recommended ac operating conditions (continued) (0c t case + 85c; v dd q , v dd = 1.283v C 1.45v ) ac characteristics 12800 cl11 10600 cl9 par ameter symbol min max min max unit exit reset from cke high to a valid command t xpr max 5nck, t rfc + 10ns - max 5nck, t rfc + 10ns - t ck begin power supply ramp to power supplies stable t v ddpr - 200 - 200 ms reset# low to power supplies stable t rps 0 200 0 200 ms reset# low to i/o and rtt high - z t ioz - 20 - 20 ns exit precharge power - down to any non - read command t xp max 3nck,6ns - max 3nck, 6 ns - t ck cke minimum high/low time t cke max 3nck, 5 ns - max 3nck, 5.625ns - t ck temperature sensor with seria l presence - detect eeprom temperature sensor with serial presence - detect eeprom operating conditions parameter / condition symbol min max unit supply voltage v ddspd +3 +3.6 v supply current: v dd = 3.3v i dd +2.0 ma input h igh voltage: logic 1; scl, sda v ih +1.45 v ddspd +1 v input low voltage: logic 0; scl, sda v il - 550 mv output low voltage: i out = 2.1ma v ol - 400 mv input current i in - 5.0 5.0 a temperature sensing range tbd tbd c temperature sensor accuracy tbd tb d c s c l s d a e v e n t s a 2 s a 1 s a 1 s a 0 s a 0 e v e n t w p / r 1 0
data sheet rev.1.0 21.11.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 12 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 a.c. characteristics of temperature sensor v cc = 3.3 v 10%, t a = ?40c to +125c symbol parameter / condition min max unit f scl scl clock frequency 10 400 khz t buf bus free time between stop and start 1300 ns t f sda fall time 300 ns t r sda rise time 300 ns t hd:dat data hold time (accepted for input data) 0 ns data hold time (guaranteed for output data) 300 900 ns t h:sta start condition hold time 600 ns t high high period of scl 600 ns t low low period of scl 1300 ns t su:dat data s etup time 100 ns t su:sta start condition setup time 600 ns t su:sto stop condition setup time 600 ns t timeout smbus scl clock low timeout 25 35 ms t i noise pulse filtered at scl and sda inputs 100 ns t wr write cycle time 5 ms t pu power - up delay t o valid temperature recording 100 ms temperature characteristics of temperature sensor v cc = 3.3 v 10%, t a = ?40c to +125c parameter test conditions/comments max unit temperature reading error class b, jc42.4 compliant +75c t a +95c, active r +40c t a +125c, monitor range 40c t a +125c, sensing range 1 ja junction - to - ambient (still air) 92 c/w 1 power dissipation is defined as p j = (t j ? t a )/ ja , where tj is the junction temperature and ta is the ambient temperature. the thermal resistance value refers to the case of a package being used on a standard 2 - layer pcb. slave address bits of temperatur e sensor device device type identifier select address signals r/w# b7 1 b6 b5 b4 b3 b2 b1 b0 eeprom 1 0 1 0 a 2 a 1 a 0 r/w# temp. sensor 0 0 1 1 a 2 a 1 a 0 r/w# 1 the most significant bit, b7, is sent first.
data sheet rev.1.0 21.11.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 13 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 serial presence - detect matrix byte byte descr iption 12800 cl11 10600 cl9 0 crc range, eeprom bytes, bytes used 0x92 1 spd revison 0x1 1 2 dram device type 0x0b 3 module type (form factor) 0x03 4 sdram device density & banks 0x0 3 5 sdram device row & column count 0x1 9 6 module nominal voltage, v dd 0x0 2 7 module ranks & device dq count 0x01 8 ecc tag & module memory bus width 0x03 9 fine timebase dividend/divisor 0x 11 10 medium timebase dividend 0x01 11 medium timebase divisor 0x08 12 min sdram cycle time (t ck min ) 0x0 a 0x0 c 13 byte 13 rese rved 0x00 14 cas latencies supported (cl4 => cl11) 0x f e 0x7 e 15 cas latencies supported (cl12 => cl18) 0x00 16 min cas latency time (t aa min ) 0x69 17 min write recovery time (t wr min ) 0x78 18 min ras# to cas# delay (t rcd min ) 0x69 19 min row active t o row active delay (t rrd min ) 0x30 20 min row precharge delay (t rp min ) 0x69 21 upper nibble for t ras & t rc 0x11 22 min active to precharge delay (t ras min ) 0x18 0x2c 23 min a ctive to active/refresh delay (t rc min ) 0x8 1 0x95 24 min refresh recovery de lay (t rfc min ) lsb 0x0 0 25 min re fresh recovery delay (t rfc min ) msb 0x0 5 26 min int ernal write to read cmd delay (t wtr min ) 0x3c 27 min interna l read to precharge cmd delay (t rtp min ) 0x3c 28 min four active window delay (t faw min ) msb 0xf0 0x01 29 m in four active window delay (t faw min ) lsb 0xf0 0x2c 30 sdram device output drivers supported 0x8 3 31 sdram device thermal & refresh options 0x0 5
data sheet rev.1.0 21.11.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 14 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 byte byte description 1 28 00 cl11 10600 cl9 32 ddr3 - module thermal sensor 0x8 0 33 - 59 bytes 32 - 59 reserv ed 0x00 60 module height (nominal) 0x0f 61 module thickness (max) 0x11 62 reference raw card id 0x0 1 63 address mapping edge conector to dram 0x00 64 - 116 bytes 64 - 116 reseved 0x00 117 module mfr id (lsb) 0x83 118 module mfr id (msb) 0 xda 119 module mfr location id 0x01 (swi t zerland) 0x02 (germany) 0x03 (usa) 120 module mfr year x 121 module mfr week x 122 - 125 module serial number x 126 - 127 crc 0 x 378b 0x e 255 128 - 145 module part number "s l n0 2g64d 2b k 1mt - xx" 146 module die rev x 147 module pcb re v x 148 dram device mfr id (lsb) 0x80 149 dram device mfr (msb) 0x 2c 150 - 175 mfr reserved bytes 150 - 175 0x00 176 - 255 customer reserved bytes 176 - 255 0 xff part number code s l n 0 2 g 64 d 2 b k 1 mt - d c * r ** 1 2 3 4 5 6 7 8 9 10 11 12 13 14 *rohs compl. swissbit ag ddr3 - 1600 m t/s sdram d dr 3 l 204 pin sodimm chip vendor ( micron ) depth ( 2 gb) 1 module rank width chip rev. k pcb - type ( s3d3b101 ) chip organisation x8 * optional / additional information ** t= thermal sensor
data sheet rev.1.0 21.11.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 15 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 revision history revision changes date 1.0 initial revision 21 . 11 .2012
data sheet rev.1.0 21.11.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 16 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 locations swissbit ag industriestrasse 4 ch C 9552 bronschhofen switzerland phone: +41 (0)71 913 03 03 fax: +41 (0)71 913 03 15 _____________________________ swissbit germany gmbh wolfener strasse 36 d C 12681 berlin germany phone: +49 (0)30 93 69 54 C 0 fax: +49 (0)30 93 69 54 C 55 ________ _____________________ swissbit na, inc. 1117 e plaza drive unit e suites 105/205 eagle, id 83616 usa phone: +1 208 258 - 6254 fax: +1 208 938 - 4525 _____________________________ swissbit japan, inc. 3f core koenji, 2 - 1 - 24 koenji - kita, suginami - ku, tokyo 1 66 - 0002 japan phone: +81 3 5356 3511 fax: +81 3 5356 3512 ________________________________
data sheet rev.1.0 21.11.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 17 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 declaration of conformity we manufacturer: swissbit ag industriestrasse 4 ch - 9552 bronschhofen switzerland declare under our sole re sponsibility that the product product type: 2g b ddr3l sodimm brand name: swissmemory? product series: ddr3l sodimm part number: sln02g64d2bk1mt - xxxrt to which this declaration relates is in conformity with the following directives: 2002/96/ec category 3 (weee) following the provisions of directive restr iction of the use of certain hazardous substances 2011/65/eu swissbit ag, november 2012 manuela k?gel head of quality management

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